BenchWeave mock — Logic analyser (class-logic

Device overview

Veridian LA-32 `· veridian.la32`

Armed · waiting for triggerConnected

Controller leasebench-01Renews in 42 sFPGA imagela32-fpga.bin · slot 0 · 9298a5ea…

advisory

0xE0

armed · pre-fill 11 · 1 s

neutral

100 MHz

Set 100 MHz

timing mode · internal clock

neutral

1.50 V

Set 1.50 V

DAC code 578 · all channels

neutral

1024 samples

50% pre-trigger · 1 s

success

25.000 MHz

counter ch 0 · ×10 Hz res

2048 samples acquired → 400 drawn · 100 MHz · capture timeΔt A→B 2.52 µs

Level	Condition	Then
1	D0 ↓ (CS#)	trigger
2	unused	—
3	unused	—
4	unused	—

Apply unavailable: sequencer register packing not yet recovered (open item)

Advisory · Status 0xE0: armed, pre-trigger buffer filling. Drain starts when bit 0 sets.

Device overview

Veridian LA-32 `· veridian.la32`

Armed · waiting for triggerConnected

Controller leasebench-01Renews in 42 sFPGA imagela32-fpga.bin · slot 0 · 9298a5ea…

advisory

0xE0

armed · pre-fill 11 · 1 s

neutral

100 MHz

Set 100 MHz

timing mode · internal clock

neutral

1.50 V

Set 1.50 V

DAC code 578 · all channels

neutral

1024 samples

50% pre-trigger · 1 s

success

25.000 MHz

counter ch 0 · ×10 Hz res

2048 samples acquired → 400 drawn · 100 MHz · capture timeΔt A→B 2.52 µs

Level	Condition	Then
1	D0 ↓ (CS#)	trigger
2	unused	—
3	unused	—
4	unused	—

Apply unavailable: sequencer register packing not yet recovered (open item)

Advisory · Status 0xE0: armed, pre-trigger buffer filling. Drain starts when bit 0 sets.

Veridian LA-32 · veridian.la32

Veridian LA-32 · veridian.la32

Veridian LA-32 `· veridian.la32`

Veridian LA-32 `· veridian.la32`